Latest ADCs will cut IF sampling down to nanoseconds

By Rob Hoyecki

February 23, 2010

Why receiver systems are poised for noticeable upticks in range, sensitivity, and selectivity.

Chip shipments on the upswing

By Will Strauss

February 23, 2010

What was top of mind for Will following CES?

Q4 sees buys, mergers, and a niche player worth watching

Samsung rolls out fastest Cortex-A8 chip

Compressing ADCs defuses data rate explosion in Data Acquisition Systems

By Daniel Kreindler

February 22, 2010

If there were a DAS Olympics, algorithms competing in the "Compression for Medical/Wireless" event would be among the fastest.

A low-cost, on-site, reconfigurable client DAQ system

Data acquisition with embedded FPGA processing - the perfect recipe for high performance

Joint FPGA-DSP grab, squeeze, and send effort sees video compression success

By Tim Klassen

December 18, 2009

Adding an FPGA to a team that includes a hybrid DSP device with a general-purpose CPU and DSP engine makes for a productive take on interfacing with numerous dissimilar video standards, compressing them to a common standard, and transmitting the result over an Ethernet link.

Video: Audience, Inc: Cell Phone Noise Reduction Based on the Human Hearing System

Video: Winner in low-power HD video designs

DC-HSPA+, MediaTek's rise, and training wheels

By Will Strauss

December 17, 2009

Will examines several reasons MediaTek looks to be more of a contender as 2010 Q1 begins.

Taming Software-Defined Radio: A graphical user interface for digital communication system prototyping

By Michael J. Leferman and Alexander M. Wyglinski

December 17, 2009

Dream Stream: Getting around what would have been an arduous learning curve by using Simulink for streaming access to the Universal Software Radio Peripheral 2 (USRP2)

E-cast: Secure Operating Systems and Tools for Next-Generation Software Defined Radios

White Paper: Digital Receiver Handbook: Basics of Software Radio

For floating-point processing, new choice arrives with the new decade

By Rob Hoyecki

December 17, 2009

Rob outlines several reasons developers addressing COTS military signal processing have reason to consider the Intel Core i7 micro-architecture.

Multi-mode sensor processing on a dynamically reconfigurable massively parallel processor array

White Paper: Integrated VXS SIGINT Digital Receiver/Processor

OpenVPX and high-speed interconnects usher in a new era of highly scalable DSP systems

By Rob Hoyecki

November 24, 2009

Hinderances to building large-scale DSP systems are falling by the wayside.

Acceleration software brings supercomputing to the desktop

Intel tries DSP again...using a "soft" approach

By Chris A. Ciufo, Editor

November 24, 2009

Software is key to Intel's DSP plans.

Performance, flexibility, and efficiency make the case for market-specific DSPs

Portrait of a power miser: Open-architecture DSP core teams with a number-crunching accelerator for audio apps

Unraveling debug and design verification snags

By Paul Bradley

November 24, 2009

Growing FPGA complexity need not equal a corresponding growth in costs or time to market.

White Paper: ISE Design Suite 11.1: Creating the First User-Specific FPGA Design Environments

Video: FPGA Design & Verification using Agilent SystemVue and LTE libraries

Tackling Linux size, modularity, and GPL issues

By Kim Rowe

November 24, 2009

Kim outlines options for developers facing proprietary kernels and OSs that can substantially limit future architectural choices, driving up costs and reducing profits.