At the system level, engineers are accustomed to making tradeoffs among the three “Ps:” performance, power consumption, and price. At the chip level, though, many designers find these tradeoffs are challenging to make, and with today’s highly integrated DSPs, a fourth P – peripherals – is just as important as the other three. By now the benefits of integration are well known to engineers: fewer chips and fewer interconnects, a smaller printed circuit board that’s easier to lay out, more on-chip memory to eliminate data bottlenecks, reduced power, and lighter weight – all of which translate into faster time to market and lower overall system costs. When selecting the right DSP, however, it’s not simply a matter of finding the least expensive chip. You must pick the System on a Chip (SoC) that has the optimal peripheral mix to best meet system and application space requirements. The issue of integration raises a number of important questions addressed in this article.
Peripheral tradeoffs
System developers need to know when and where peripheral tradeoffs can be advantageous. For instance, a DSP used for a portable media player might need the correct network, memory, and storage peripherals. On the other hand, a DSP used for video infrastructure needs top performance and high bandwidth peripherals. No longer is it just a choice among processor cores, the system designer must consider the peripheral needs of his or her application space.
When creating these diverse integrated DSPs, chip suppliers can apply a number of factors to improve system design. Obviously, the mix of peripherals and the addition of fixed-function accelerators set the level of integration. Suppliers can use different process technologies and add transistors optimized for either low power or high performance. Yet other factors include voltage levels, clock rates, package design, and even the layout of balls on the package.
The system designer, in turn, has some decisions to make – creating a product is not simply a matter of placing a couple of chips on a board. One important aspect is system partitioning, in other words, which peripherals should be on or off chip? For instance, is there a need for storage connectivity interfaces on chip? Or can customers easily incorporate external storage interfaces off chip? Even those engineers who closely follow the latest chip offerings are constantly amazed at the level of integration that each new generation of devices brings, and the trend will only continue. Each choice requires a careful consideration of tradeoffs among many factors including cost, performance, and size.
Key questions to ask chip
suppliers about integration
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| When selecting a chip and a supplier, designers should keep a number of questions in mind. Here are some suggested questions to consider:
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- Which peripherals are available on a given device?
- Is there an existing mix that closely matches requirements?
- Must performance tradeoffs be made with onboard peripherals?
- Are some peripherals better placed off the chip?
- If there’s no exact match of peripherals to application requirements, can the on-chip processor be programmed to perform the needed extra functions?
- Would the application benefit from multiple cores, such as a DSP/RISC combination?
- How must tasks be assigned to the different cores in an optimal fashion?
- How easy is it to move data among the cores and on-chip peripherals?
- What are the system power implications? Does the chip require a number of voltages, and how well does it do at generating them, such as from a single supply voltage?
- Does the chip supplier have a roadmap that tells what integration to expect in the future?
- Do the device architectures lend themselves to future upgrades with minimal impact on the overall system design?
- Can the chip supplier execute complicated chip designs on schedule, and then ramp successfully to production as process geometries get smaller and smaller?
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Client video and audio applications
The client video and audio market is constantly evolving as end customers continue to demand the latest technology at a great price. When selecting the correct SoC, a system designer needs to take into consideration the needs of the market. Choosing an SoC with the correct peripheral mix can help reduce the size, power consumption, and ultimately the price for the end customer.
In this market, we are seeing customers demand quality video with frame rate, resolution, and format flexibility. To address this need, system designers must think about how peripherals can be used to meet this market demand. For example, a video-programmable DSP provides video algorithm flexibility but should be coupled with the correct memory, storage, and video interfaces to efficiently feed the data in and out of the system.
A key component of a client video and audio appliance is a video-programmable DSP that provides quality video and flexibility. With consumer demand for a large variety of video/audio algorithms, such as MPEG-4, WMV9, MPEG-2, H.264, and so forth, the ability to support them all becomes a differentiating factor. In addition, a customer typically will want to utilize legacy code or go to a third-party vendor for CODEC support. This shortens time to market and reduces the development cost for the OEMs and ultimately the system cost for the end customer.
However, the video-programmable DSP still requires the correct set of memory and storage peripherals to do its job. Besides the traditional need for both L1 and L2 cache, an SoC for client video and audio requires a fast External Memory Interface (EMIF). For example, TI’s TMS320DM642 currently integrates a 64-bit SDRAM interface. However, with memory interfaces continually improving, silicon providers must be dedicated to integrating the latest memory innovations such as DDR2.
Besides external memory, system designers must also consider the need for network-enabled peripherals. There are a lot of reasons why network capability could be attractive. Consumers want the capability to play the wide variety of media content on the Internet. System designers might want to utilize the robust Ethernet standard as a data backplane. Unfortunately, in the past, adding an Ethernet Media Access Controller (EMAC) required an external EMAC connected to a data bus. The resulting design was usually large in size, costly, and complex. TI’s TMS320DM642 integrates a 10/100Base-T EMAC on-chip (see Figure 1), allowing system designers to save board space and reduce system cost.
Figure 1. Click each to zoom.
In the future, SoCs will continue to become more highly integrated as consumers demand more memory and storage options. For example, with the popularity of digital cameras, OEMs demanded MultiMedia Card and Secure Digital interfaces, such as those found on the TMS320VC5509A. In addition, USB 2.0 high-speed (480 Mbps) and hard drive ATA glueless interfaces will enable consumers to transfer data at fast rates and store data locally.
A final peripheral of great importance to this market is the video port. A video port on an SoC allows for a glueless interface to common video decoder and encoder devices. In the past, a system designer would need an FPGA, or other logic, to parse video data from a system into a video encoder or video decoder. At that time, SoCs did not have peripherals that understood the data formats found in standard video encoder and decoder devices.
The TMS320DM642 solved this problem by introducing three 20-bit configurable video ports. These video ports’ peripherals support multiple resolutions and video standards (for example, CCIR601, ITU-BT.656, BT.1120, SMPTE 125 M, 260 M, 274 M, and 296 M). These features enabled system designers to remove some FPGAs from their systems, further reducing system cost and board size.
However, the video ports on the TMS320DM642 have only tipped the iceberg. In the future, video ports could possibly incorporate the ability to capture CCD/CMOS images and output to LCDs or on-screen displays gluelessly. In addition, video ports might integrate digital analog converters, making it possible to output standard analog video such as NTSC/PAL and Composite S-Video.
Infrastructure applications
Infrastructure applications require a different peripheral mix than client video and audio. They share many of the same system requirements but are also concerned about high channel densities and throughput along with low cost per channel. The right peripherals and memory go far towards reaching these goals.
Optimized for telecom infrastructure applications, the 90 nm, 1 GHz TMS320C6416T includes among its many peripherals three Multichannel Buffered Serial Ports (McBSPs); a Universal Test and Operations PHY Interface for ATM (UTOPIA) slave port; a host-port interface; and a PCI interface (see Figure 2). These subsystems implement industry-standard interface schemes that can eliminate many external chips and save a system designer many dollars.
Figure 2. Click to zoom.
These peripherals, of course, do not come for free as they take up chip area and power, but the system payoff can be big. For instance, the C6416 also provides a Viterbi Decoder Coprocessor and a Turbo Decoder Coprocessor. These two alone account for roughly 10 percent of the chip area and 10 percent of the total power, quite acceptable for applications that demand significant speeds in channel-decoding operations. With these coprocessors a system can improve its channel throughput by four times, which is well worth the 10 percent increase in size and power (Figure 3).
Figure 3. Click to zoom.
While this was a great improvement, customers continued to demand higher channel densities, throughput, and lower cost per channel. TI addressed this demand by launching the 90 nm 1GHz TMS3206455 in May 2005. Taking advantage of increased integration, the TMS3206455 incorporates Serial RapidIO (SRIO), a gigabit EMAC, DDR2, and 2 MB of L2 memory. With this peripheral mix, customers can create high performance video infrastructure, telecom infrastructure, and medical/imaging applications.
The C6455 DSP’s integrated industry-standard SRIO bus decreases overall system cost by reducing the need for additional devices used for switching and processor aggregation. Supported by an industry association of leading device, system, and software manufacturers, the SRIO interconnect enables high-speed, packet-switched, peer-to-peer connectivity. SRIO thus makes it much easier to implement multiprocessing, providing a performance breakthrough for multichannel implementations on multiple processors. For video infrastructure applications, a 1x SRIO link is fast enough to send High Definition (HD) 1080i raw video between devices, and a 4x SRIO link can easily send HD 1080p raw video between devices with bandwidth to spare. The use of SRIO in infrastructure applications with large “DSP farms” will allow the reduction of system cost (device count, board size and/or device cost) for OEM customers.
Besides SRIO, the C6455 DSP also incorporated other high bandwidth peripherals such as the gigabit EMAC, DDR2, and 2 MB of L2 memory. The gigabit EMAC has ten times more Ethernet bandwidth than previous C64x devices. As customers continue to demand faster network speeds, TI is committed to exploring options to integrate new network controllers. In addition, the 500 MHz DDR2 external memory interface provides twice the throughput, allowing system designers to pump in data at a faster rate. Finally, the 2 MB of L2 memory is twice that found on the C6416T DSP. The extra memory enables extra performance, further reducing the price per channel in infrastructure applications.
Keep your eyes open
Integration will certainly continue. The benefits of reduced system cost, complexity, and board size cannot be ignored. As the client video and audio market continues to mature, there will be more functions to incorporate onto the SoC, and the functionality of existing peripherals will constantly be improved. For example, there is demand for robust standard OS application flexibility in the client video and audio market moving forward.
In addition, as DSPs continue to increase in performance, video infrastructure, and telecom infrastructure, medical/imaging customers will continually ask for ways to increase bandwidth. In order to answer their demand, silicon providers will continually look at new network, high-speed bus, and memory innovations as opportunities to integrate and further reduce costs.
No matter what types of systems developers work with – whether audio, video, RF, telecom infrastructure, or even industrial applications – they should keep tabs on industry trends, because new SoCs are coming off the fab lines at an increasing rate. There could well be one that would cut the development time and cost of those systems.
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