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OSP editors weigh in on programmable logic
Three short commentaries on programmable logic, with your comments welcomed.
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Three short commentaries on programmable logic: "My FPGA observations come back to haunt me," By Chris A. Ciufo, "No more excuses," By Don Dingee, and "Complexities of using PLDs," By Jerry Gipper.
My FPGA observations come back to haunt me
Recently, several companies blasted me for my complaints in the DSP-FPGA.com editorial “2 Trends I Didn’t See”. Well gosh, here’s where I make amends and set the record straight on FPGA tools and cell phone trends.
Fire One! Zeligsoft took issue with my comments lamenting no Eclipse-like “drag and drop” system creation and validation tools. Their spokeswoman scolded me that “Zeligsoft CE does take a system-level approach, creating and validating Software Defined Radio system deployments.” The company now has partnerships with well known ESL software companies including Green Hills, the Government of Canada, The MathWorks, SCA Technica, Objective Interface Systems, and others. Give ’em a cigar.
Fire Two! Gedae, who touts “effortless transition between design and hardware” lobbed a Letter to the Editor taking me out behind the woodshed concerning multi-core CPUs and system design ease and reuse. They retorted that build-time software partitioning to heterogeneous processors with Gedae aids in “spiral development…with hardware abstraction.” So ok, clearly there’s no need to code FPGAs down at the “metal.”
Fire Three…and Four! By the time you read this, QuickLogic will have just announced their ArcticLink product line of inexpensive, ultra low-power FPGAs for cell phones and other portable doodads. They argue that the FPGA need not replace the system CPU, but will become the intersection between the CPU and the intelligent peripherals like Wi-Fi, DRM, TV Out, and USB. Similarly, Xilinx’s brand new Spartan-3AN includes Flash and specifically targets low power handhelds. Go figure.
So all this feedback implies that my trend predictions were correct: I just didn’t see them.
Comments:
Some bosses may have figured out buying car insurance, but maybe not the concept of using FPGAs. I’ve heard various cave-dwelling bosses grunt, “FPGAs are too …”
“…slow.” 10 Gbit SERDES capability is here. So are 550 MHz multiplier clocks. And partial reconfiguration times in microseconds. They’re plenty fast, and getting faster.
“…hard to design.” Sure, if you’ve never programmed a number into your cell phone. Tools are solid and getting better daily – everything from VHDL and C language tools to graphical system design.
“…expensive.” If you’re building 10 or 1,000,000 units, debate away. But for volumes in between, FPGAs present a good life cycle cost – especially considering the time to get a complex ASIC can easily be two years.
“…hard to support.” FPGAs are the “last inch” on many single board computers for flexible I/O. Granted, end customers might try to put something in an FPGA on your board, not be able to get it to work, and call for support. Give customers the right tools and they can usually get it right. Or, your competitors will.
Got a boss grunting these excuses? Have them crawl out of their cave and read this article and more, on this website.
Comments:
Hardware designers have used Programmable Logic Devices (PLDs) for many years, often as glue logic or to fill in feature gaps. As the logic became competitive in performance, capacity, and price, system designers began to make PLDs available for end users to process their own application-specific algorithms. Unfortunately, this was no easy task as the tools to develop, test, and even download these algorithms were not very effective. Tools that could implement the details while the programmer worked at an abstract level became essential.
Several concerns arise as end users implement these devices. PLDs are usually programmed by hardware engineers, many who lack the right experience. The PLDs are programmed like software, with complexity and problems to match, but are ultimately hardware. Plus, current implementation and quality assurance activities may not be adequate for these devices’ complexity.
Luckily, new advances have simplified these tasks. But is it enough, or does the EDA community have more work to do? The logic suppliers claim they have the solutions, but what does the user community have to say? Send us your comments and we will share your experiences.


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