SRS chose 32-bit floating-point SHARC processors from Analog Devices, Inc. (ADI) as the platform for its CS II algorithms because of the processor’s high-performance, rich audio feature set, and well-earned reputation in the audio market.

It used to be that surround-sound audio experiences were confined to movie theater settings. Then along came multi-channel encode/decode systems, enabling theater-quality sound in the home. This was great when media was confined to a few well-defined sources, but today, content production, transmission, and storage of media spans such a wide range of channel configurations and compression protocols that it can be a real challenge to deliver high quality surround sound.

SRS Labs Circle Surround (CS) II encode/decode technology speaks to this challenge, enabling media formats and A/V setups that previously could only deliver right/left stereo sound to produce full multi-channel surround sound. Plus, CS II is quickly becoming the standard for the creation, production, and broadcast of up to 6.1 discrete channels of surround sound over traditional two-channel distribution systems, including television commercials, sports broadcasting, network shows, cable and satellite transmissions, and standard music CDs. CS II decoding supports numerous product applications, including home theater, PCs, automobile stereos, and wireless streaming, allowing consumers to take advantage of their multiple speaker systems, including older VHS tapes, FM radio broadcasts, stereo music CDs, and computer games.

As you might imagine, SRS’ CS II algorithms are computationally demanding, and as such, require a processor powerful enough to handle sophisticated mathematical equations. To make its technology available for any product manufacturer, SRS teamed with ADI for a turnkey solution based on SHARC processors. The processors, which feature an integrated set of audio features and enough power to process the CS II algorithms and other functions, were a good selection to drive CS II solutions in both the pro audio and home entertainment markets.

SRS patented post-processing techniques bundled with CS II solutions include: SRS Dialog Clarity, which improves the intelligibility of dialog, as it can often be difficult to hear clearly over explosions, music soundtracks, and other sounds; SRS TruBass , which works with any size speaker, including headphones and earbuds, enabling listeners to perceive a heightened sensation of lower bass tones beyond the natural low frequency capabilities of the speaker itself; and SRS Focus (for CS Automotive), which raises the audio image from speakers mounted low in the doors of automobiles and provides “mix to rear” functionality to balance the surround image for the rear passengers while maintaining an excellent surround field for those in front.

Figure 1: Block diagram of a SHARC processor

ADI’s 32-bit floating-point SHARC processors are based on a Super Harvard architecture that balances exceptional core and memory performance with outstanding I/O throughput capabilities. In addition to satisfying the demands of the most computationally intensive, real-time signal-processing applications, SHARC processors integrate large memory arrays and application-specific peripherals designed to simplify product development and reduce time to market.

The right audio features Architecturally, SHARC processors had all of the audio features SRS needed, supporting all of the standard audio in/out interfaces as well as easy analog-to-digital, digital-to-analog conversion, as referenced in Figure 1.

The SHARC processor’s audio-specific peripherals, broadly described as the Digital Audio Interface (DAI), are functional blocks that may be connected to each other or to external pins via the signal routing unit (SRU). Peripherals connected through the SRU include as many as six high performance synchronous serial ports, SPI ports, an input data port (IDP), precision clock generators, timers, and others. The combination of the serial ports and IDP means that SHARC processors can support up to 20 stereo I2S channels, providing up to 40 channels of audio (which is important as the number of speakers and input sources is increasing in audio applications). Additional value-added peripherals include an S/PDIF transmitter/receiver and 8-channel asynchronous sample rate converter. Audio-specific peripherals such as these allow manufacturers to leverage a single hardware design for multiple products with various I/O requirements.

Encoding/Decoding

CS II Encoder Algorithm Figure 2: Block diagram of the CS II Encoder Algorithm (click image to zoom by 1.3x) A1 and A4 are input summing amplifiers. They combine the main left and right signals with the center input and the Low Frequency Effects (LFE) input, which accommodate LFE sounds, such as explosions. The output of the two amplifiers (which now contains the left, right, center, and LFE information) is then applied to constant phase filter banks F1 and F4. The output is then passed to output summing amplifiers A5 and A6.  Next, summing amplifiers A2 and A3 combine the surround back input with the surround left and right inputs. The output of these amplifiers is then fed to constant phase networks F2 and F3 to encode the surrounds in quadrature with the main channels, which is required to prevent signal cancellation. The surround signals are then mixed antiphasically into the left/right output.  A “surround positional bias generator” analyzes the ratio of the left and right surround signal level to produce steering signals. The steering signals are then applied to multipliers M1 and M2, which modulate the level of the surround mix into the opposing left or right output. CS II Decoder Algorithm Figure 3: Block diagram of the CS II Decoder Algorithm (click image to zoom by 1.3x) This block diagram shows the overall signal processing structure of the core CS II decoder. The first stage takes place in the input matrix. The algorithm derives the sum and difference signals from the left/right input, producing phase-inverted left and right outputs. These signals will be used throughout the rest of the decoding process. Initial processing of CS II steering information takes place in the Level Data Processing block. This information is then used by the Steering Generator to direct signals to the appropriate channels. Level data is calculated and updated every 128 audio samples. The CS II decoder makes use of the level imbalance in the out-of-phase surround material to “steer” the surround information left or right. Dual-band steering is utilized in the decoder to stabilize the surround steering and to minimize “pumping” effects between the surrounds. The CS II decoder algorithm also includes post-processing techniques to enhance the audio experience, such as bass performance, and to address problems, such as dialog clarity.

For more information about CS II and CS Automotive, visit the SRS website or contact Alan Kraemer.

Alan D. Kraemer has served as Chief Technology Officer of SRS Labs since January 2005. He has also served as Executive Vice President, Technology and Business Development since June 2004. Prior to this, he has served as Vice President of Engineering since April 2000, and Director of Engineering since February 1994. In addition, Alan served as President of Sierra Digital Productions, Inc., a compact disc production and recording company, since August 1989. Prior to joining SRS Labs, he served as Senior Vice President of Engineering of De LaRue Printrak, a manufacturer of automatic fingerprint identification systems, Vice President of Engineering for AST Research, a personal computer manufacturer, Vice President of Engineering with Point4 Data Corporation, and as Director of Software Engineering of Northrop Electronics.

SRS Labs

2909 Daimler Street Santa Ana, CA 92705 Phone: 949-442-1070 Email: AlanK@srslabs.com Website: http://www.srslabs.com