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The debate over FPGAs as a viable alternative for ASICs and ASSPs has been ongoing for almost a decade. Industry analyst reports from iSupply, Gartner Dataquest, and others have well established the trend in decreasing ASIC design starts and in increasing FPGA design starts. Next-generation platform FPGA devices based on 90nm have greatly expanded high-performance processing and system integration options and continue to lower ASIC design starts as designers define additional application solutions.
The debate over FPGAs as a viable alternative for ASICs and ASSPs has been ongoing for almost a decade. Industry analyst reports from iSupply, Gartner Dataquest, and others have well established the trend in decreasing ASIC design starts and in increasing FPGA design starts. Next-generation platform FPGA devices based on 90nm have greatly expanded high-performance processing and system integration options and continue to lower ASIC design starts as designers define additional application solutions.
With the beginning of the new millennium, the debate continued with the introduction of platform FPGAs. These high-performance devices, with their flexible device integration capability, programmable I/O, and significantly lower overall design cost, helped to usher in and establish System-On-a-Chip (SoC) design methodology and quickly assumed innumerable ASIC SoC designs. The addition of high-performance RISC CPUs, block RAM, multi-gigabit, high-speed serial I/Os, dedicated DSP functions, and other system enhancements introduced technological advances, which further solidified the rise of platform FPGAs over their ASIC SoC counterparts. However, in order to get the high-performance DSP processing or required connectivity features for a specific domain of applications, designers typically purchased the largest, more costly devices. The largest parts had the biggest helpings of advanced features, and the smaller parts had reduced portions of the same.
New breed offers more choices
A new breed of domain-optimized platform FPGAs promise multidimensional application scaling based on required features and cost goals. By combining the economic benefits of an innovative, columnar architectural approach with advances in process technology (90nm/300mm), programmable logic vendors are poised to move beyond the $5.1-billion programmable logic market to capture additional share in the $84-billion ASIC and ASSP markets (Source: Gartner Dataquest 2007). Thanks to a columnar architectural approach, an FPGA vendor can now cost-effectively develop multiple FPGA platforms, each with different combinations of feature sets. This means a designer can optimize a specific platform for a certain domain of applications, such as logic, DSP, connectivity, and embedded processing, to meet application requirements previously delivered only by ASICs, ASSPs, and similar devices, while remaining programmable at heart.
Not only does a designer or design team have choices when selecting the ideal platform, but also they have choices when picking the size of a device with the right feature mix to best achieve needed capability and performance at the lowest possible cost.
The unique flexibility and ability to create optimal application-domain sub-systems sets even higher standards for FPGAs. Devices that are both hardware and software programmable enable more flexible implementation options than ASICs or ASSP devices. The ability to reinvestigate and change or enhance system architecture anytime in the development process gives designers the ultimate tool kit to meet application requirements. This flexibility becomes paramount in the situation of emerging or competing standards. Designers can use this same capability to evolve hardware in the field to meet new requirements or avoid expensive hardware upgrades.
The “total cost” advantage
FPGAs have demonstrated a clear and consistent trend in reducing cost and making their technology more suitable for a wider range of applications. The combination of using 90nm silicon fabrication technology together with 300mm wafers results in a cumulative effect of increasing the number die per wafer five times over previous generation devices. Increasing the die per wafer together with architectural integration enables substantially lower system cost.
How people use technology throughout the world clearly demonstrates an important and often overlooked component in the economic advantage of programmable logic; no two people use the same technology, systems, or software, nor do they subscribe to or want the same content.
Substantially higher cost and longer design times for ASICs and ASSPs relegate their primary uses to proven lower-risk, very-high-volume applications. The rapid and significant increase in ASIC development costs clearly tips the advantage to using increasingly capable platform FPGAs in both bleeding- and leading-edge applications. The overall cost benefit of zero NRE pushes the high-volume ASIC or ASSP crossover point upwards, locking in FPGAs like never before.
Revolutionary ability of FPGAs
Domain-optimized platform FPGAs are revolutionary in their ability to accelerate the deployment of FPGA technology into many more application areas. Soon, the combined leverages of reduced risk, dramatically shorter design cycles, and zero NRE will move all but the highest-volume, highest-performance, or lowest-power applications away from cell-based ASIC implementation toward more flexible, forgiving architectures like today’s domain-optimized FPGAs.
