The use of FPGAs in many applications is rapidly increasing. With the attributes of reconfigurability and design-to-working part times much faster than those of ASICs, FPGAs offer avionics engineers advantages not available in mask-programmable silicon platforms. However, SRAM-based FPGAs are susceptible to particle-induced SEUs, which make their deployment in avionics problematic. The solution to this dilemma lies in the use of both FPGAs and a structured ASIC for complete system development, with a clear migration path using a single tool flow and suite. Using an FPGA to validate an initial design and then migrating from the FPGA to a structured ASIC reduces cost, power, and system susceptibility to SEUs.