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XtendWave is a fabless semiconductor company that develops and licenses modulation, encoding, and security technology and products. To model our designs, we start with MATLAB. However, to successfully implement a design in MATLAB, we must make sure that current algorithm synthesis technology can manage it. I’ll describe in this article how we go about this process.
Forming a “more perfect marriage”
Although the MATLAB language is very broad in its capabilities, as is VHDL and Verilog, not all of the language is synthesizable. Therefore, the engineer must write the MATLAB code so that the AccelChip DSP Synthesis tool can synthesize it, and so the resulting RTL code will efficiently perform the required operation. This is not a limitation of the AccelChip tool, but simply a physical requirement of what the implementation engineer has to do in order to accomplish the ultimate goal.
For our design process, we start with a verified floating-point design using MATLAB and convert it into a fixed-point design with AccelChip’s auto-quantization technology. We then verify the fixed-point design to match the floating-point design, once again using MATLAB. When we verify this, we then use AccelChip to synthesize it into an RTL design that matches the fixed-point MATLAB representation targeted specifically at the Xilinx Virtex-II Pro FPGA. Next, using a Synplicity synthesis environment, we generate a net list for Xilinx place-and-route tools.
The big advantage of the AccelChip for the XtendWave tool is that smaller start-up engineering teams such as ours can generate synthesizable RTL code with a very complex level of functionality, very quickly.
Manual conversion of advanced algorithms like ours, written in the MATLAB language, typically requires a large team of implementation engineers. In addition, from my experience, this process is often plagued with mistakes and hidden bugs that take months to debug by another large team of verification engineers with a completely different skill set than the implementation engineers.
The automatic, RTL test-bench generation function built into the AccelChip DSP Synthesis tool significantly shortens the design verification phase. This is because the test bench generated by AccelChip uses the same input/output vectors that are in the MATLAB simulation to provide stimulus and to compare the output vectors from the RTL simulation.
Once the engineers synthesize and implement the design into a specific FPGA, they can use the same test bench with a simulator, such as the Aldec Riviera simulator, to verify the gate-level net list. One key feature of the test bench is the built-in parameters to control frequency and hold-time specifications once they introduce gate-level delays into the simulation process. Refer to Figure 1 for a diagram of the AccelChip DSP Synthesis workflow process.
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| Figure 1: AccellChip MATLAB Architectural Synthesis |
A new level of design is born
In my opinion, AccelChip has broken the barrier between designers and machine-generated HDL code. In the past, as a designer I would cringe at the thought of dealing with any non-handwritten HDL code by a very experienced engineer. Today, with the help of EDA vendors like AccelChip, we are seeing a new level of design and verification capability that reduces the design cycle and the time it takes to get a product to market.
