Though DSP libraries abound for AltiVec-based applications, new architectures require new potential hosts for DSP applications. Thus, new libraries providing advanced portability are integral to the equation.
FPGA power optimization brings to mind a particularly challenging game of limbo. Fred explains, however, that new design techniques can help FPGAs slip under even a power consumption limbo stick held at a tiny height.
If a clock tree falls in the forest of synchronous high-speed DSP designs, do any necessary computing functions fall with it? No, argues Doug, who makes the case for axing the clock tree to reduce power consumption by up to 40 percent in a high-performance processor.
Good PR: It's not the usual meaning. PR in this case is Partial Reconfiguration, one of two approaches to run-time reconfiguration, with the other being Software Programmable Reconfiguration (SPR), discussed here. However, with benefits including reduced power consumption, hardware reuse, obsolescence avoidance, and flexibility, Good PR could indeed be the result.
X5-COM PCI Express IO Module featuring 4 Ethernet/SRIO/Gigabit Serial PortsMORE
Analog Devices
New FireCracker Development and Reference Design PlatformMORE
Synopsys
FPGA-based Rapid Prototyping:
No Assembly Required.MORE
Product Guide
FPGA-based systems Find a comprehensive listing of FPGA-based systems at our FPGA channel, including Pentek's Model 7156 Dual 400-MHz A/D & 800-MHz D/A PMC/XMC Module, shown here.
Broadcast Schedule:
No results found. More broadcasts should be scheduled soon for this topic. Until then, try finding what you're looking for in the archive of recent broadcasts.
&w=110&fltr[]=ric|7|7&q=84)
Developers throttle the bottleneck to grab maximum I/O bandwidth using FMCs
&w=110&fltr[]=ric|7|7&q=84)
Semiconductor upturn now in sight&w=110&fltr[]=ric|7|7&q=84)
DSP library portability speeds application development&w=110&fltr[]=ric|7|7&q=84)
Design techniques for FPGA power optimization&w=110&fltr[]=ric|7|7&q=84)
Power vs. performance: The ultimate DSP design challenge&w=110&fltr[]=ric|7|7&q=84)
White Paper: FPGA Run-Time Reconfiguration: Two Approaches
&w=110&fltr[]=ric|7|7&q=84)
White Paper: Introducing the Xilinx Targeted Design Platform: Fulfilling the Programmable Imperative
)
)
)
)
)
)
)
)
FPGA-based systems
