eASIC's Innovative Structured ASIC Wins DesignVision Award

San Jose, California, February 7, 2005 -- eASIC® Corporation, a provider of Configurable Logic and Structured ASIC products, today announced that its Structured eASIC product won the DesignVision Award presented by The International Engineering Consortium (IEC). These inaugural DesignVision Awards are aimed at recognizing companies for products and services that have added a new dimension to the electronic design industry and to the society as a whole. The award ceremony was held at the DesignCon conference in Santa Clara, Calif. on February 2, 2005. The Structured eASIC was selected as most innovative and unique product in the category of “Structured/Platform ASIC, FPGA, and PLD Design Tools”.

“Receiving this award re-enforces the critical need for an affordable and predictable custom logic design solution in the nanometer design era,” said Zvi Or-Bach, eASIC Founder and CEO. “We believe that our NRE-free configurable logic technology will arrest the decline in ASIC starts and create a resurgence in logic customization across the spectrum of complexity, ranging from just a few hundred thousand gates all the way to multi-million gate SOCs. The future is exciting as we can now expect as an industry to see innovation put into practice more than ever. We have entered into a new era of cost effective hardware customization”.

Innovative Configurable Logic Technology - Structured eASIC

eASIC has a unique Configurable Logic technology implemented in its Structured eASIC products. The patented architecture consists of SRAM-based logic cells and flip-flops that are interconnected by a segmented wiring grid utilizing upper metal layers. The logic cells programming is done similarly to an FPGA, by loading a bit-stream to program the LUTs (Look-up-Tables) and initialize the flip-flops after powering up the device. The routing and interconnection is performed similar to other ASICs, but utilizes just a single via-layer for customization. Thus, a customer design is implemented on the Structured eASIC fabric by using a combination of bit-stream to program the LUTs and a single custom Via-mask for customizing the routing. Moreover, the single mask can be eliminated for prototyping and low-volume by using Direct-write eBeam. Hence, eASIC’s use of maskless lithography removes the customization tooling cost, shortens time-to-market, and adds manufacturing flexibility, allowing eASIC to provide the industry with an NRE-Free customized ASIC devices with densities, power and performance akin to a standard cell ASIC.

About eASIC

eASIC® has developed a breakthrough Configurable Logic technology aimed at dramatically reducing the overall fabrication cost and time of customized high-performance semiconductor chips. Its Structured eASIC architecture enables rapid and low-cost ASIC and SoC (System-on-Chip) designs by innovative use of proven programmable logic fabric in conjunction with single-via customizable segmented routing. As single-via generates ten times higher throughput of Direct-write e-Beam customization, it enables eASIC to offer NRE-free Structured ASIC. The Structured eASIC technology was successfully proven in silicon and validated by world-class semiconductor vendors. Partnering with industry leaders to jointly develop, manufacture and market Structured ASIC products, the company is positioned to become the preferred Structured ASIC solution.

eASIC Corporation is a privately held company, Venture Capital backed by Kleiner Perkins Caufield and Byers. Headquartered in San-Jose, California, eASIC was founded in 1999 by Zvi Or-Bach, the founder of Chip Express.

www.eASIC.com